IIT Madras, ISRO Successfully Developed and Booted Indigenous Microprocessor for Space Applications

IIT Madras and ISRO have developed and booted an indigenous aerospace-grade semiconductor chip based on RISC-V, an open-source Instruction Set Architecture. 

The ‘IRIS’ (Indigenous RISCV Controller for Space Applications) chip was developed from the ‘SHAKTI’ processor baseline. This highlights India’s efforts toward self-reliance in semiconductor technology for space applications.  

Professor V. Kamakoti, director at IIT Madras, led the SHAKTI microprocessor project at the Prathap Subrahmanyam Centre for Digital Intelligence and Secure Hardware Architecture (PSCDISHA).

The project is backed by the Ministry of Electronics and Information Technology (MeitY) under the ‘Digital India RISC-V’ (DIRV) initiative. 

IIT Madras called this a “breakthrough in India’s self-reliance in space tech” in its post on X. The post further broke down the manufacturing process and claimed that the IRIS chip “will power ISRO’s space missions, ensuring advanced fault tolerance & computing reliability.”

V. Narayanan, chairman of ISRO, also hinted that a flight test may be coming soon! Furthermore, Kamakoti also took to X to display a demo of the chip.

How was the Chip Made?

This Made-in-India processor was manufactured at SCL (Semiconductor Laboratory) Chandigarh and packaged at Tata Advanced Systems in Karnataka. The motherboard was further developed by PCB Power in Gujarat and assembled by Syrma SGS in Chennai.

“After RIMO in 2018 and MOUSHIK in 2020, this is the third SHAKTI chip we have fabricated at SCL Chandigarh and successfully booted at IIT Madras,” Kamakoti said. 

The fact that chip design, fabrication, packaging, motherboard development, assembly, software, and booting all happened within India validates the strength of the country’s semiconductor ecosystem. 

The IRIS chip is designed for a range of applications, including IoT and strategic computing needs. This effort aligns with ISRO’s goal of indigenising semiconductors for command and control systems and other critical functions in space missions.  

The ISRO Inertial Systems Unit (IISU) in Thiruvananthapuram initiated the development of a 64-bit RISC-V-based controller and collaborated with IIT Madras on specifications and design. The final configuration was tailored to meet the computing requirements of ISRO’s existing sensors and systems.  

The design also supports future expansion through multiple boot modes and hybrid memory/device extensions. Extensive software and hardware testing ensured high reliability and performance.   

Kamaljeet Singh, director general at SCL Chandigarh, highlighted the role of SCL, saying, “Fabricated in our 180 nm technology node, the processor underwent extensive design validation and testing. SCL remains committed to supporting academia and startups.”